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Software Description:
The SynaptiCAD Product Suite includes thefollowing products: TestBencher Pro, VeriLogger Extreme, VeriLoggerPro, BugHunter Pro, DataSheet Pro, WaveFormer Pro, WaveFormer Lite,Timing Diagrammer Pro, GigaWave Viewer, Vhdl2Verilog, andVerilog2Vhdl. A license is required for all versions.
TestBencher Pro is a graphical test bench generator thatdramatically reduces the time required to create and maintain testbenches. TestBencher Pro automates the most tedious aspects of testbench development, allowing you to focus on the design andoperation of the test bench. This is accomplished by representingeach bus transaction graphically and then automatically generatingthe code for each transaction.
BugHunter uses the SynaptiCAD graphical environment and supportsall major HDL simulators. It has the ability to launch thesimulator, provide single step debugging, unit-level test benchgeneration, streaming of waveform data, project management, and ahierarchy tree.
DataSheet Pro is SynaptiCAD’s top of the line timing digarameditor, providing the ultimate environment for documentationprofessionals working with multi-diagram projects. Datasheet Pro’sproject management features allow users to efficiently combinediagrams from multiple engineers into one project with uniformformatting. Using Object Linking and Embedding (OLE), users canembed timing diagrams into other publishing programs.
WaveFormer Pro is a revolutionary new rapid-prototyping EDA toolthat helps you design faster and with fewer mistakes. WaveFormerPro enables you to automatically determine critical paths, verifytiming margins, adjust for reconvergent fanout effects, and perform”what if” analysis to determine optimum clock speed. WaveFormer Proalso lets you specify and analyze system timing and perform Booleanlevel simulation without the need for schematics or simulationmodels.
VeriLogger Extreme is a completely new, high-performancecompiled-code Verilog 2001 simulator that significantly reducessimulation debug time. VeriLogger Extreme offers fast simulation ofboth RTL and gate-level simulations with SDF timing information.VeriLogger Extreme supports design libraries and design flows forall major ASIC and FPGA vendors, including Actel, Altera, Atmel,LSI Logic, QuickLogic, and Xilinx.
Installer Size: 279.33 MB
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